1. Field of the Invention
The present invention relates to a voltage generator for nonvolatile memory and, particularly, to a voltage generator for nonvolatile memory which includes a booster.
2. Description of Related Art
There is known a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) nonvolatile semiconductor storage device. The nonvolatile semiconductor storage device of this type writes or erases data by trapping electrons in a dielectric film such as a nitride film. FIG. 27 shows a MONOS memory which holds written information by trapping electrons in a nitride film 61. When writing data in a memory having the structure shown in FIG. 27, voltages of 4.5V, 5.5V and 0V, for example, are applied to a drain electrode 62, a gate electrode 63 and a source electrode 64, respectively. As a result of applying such voltages to each terminal, an inversion layer is generated immediately below the gate, so that electrons which flow from the source to the drain are generated. In the electrons flowing from the source to the drain, hot electrons which are accelerated in a depletion layer that is formed in the vicinity of the drain are generated. The hot electrons are injected from the vicinity of the drain into the gate side, so that the hot electrons are trapped in the nitride film 61. In this way, writing ends.
During writing, a large number of hot electrons are generated in the vicinity of the drain of a memory cell (cf. FIG. 27). Therefore, the electrons which are trapped in the nitride film 61 are concentrated in the vicinity of the drain of the memory cell. Then, after a certain period of time from writing, the electrons which are trapped in the vicinity of the drain move slowly in the nitride film 61. Consequently, the electrons are averaged to a certain extent and trapped in such a state (cf. FIG. 28). Accordingly, a threshold of the memory cell changes with time after writing (cf. FIG. 31). If the threshold of the memory cell significantly decreases after writing as a result of such a change, it causes a failure in proper data reading, which leads to a loss of written information.
FIG. 29 shows a MONOS memory in the case of erasing data which are accumulated in the nitride film 61. When erasing data, voltages of 5V, −3V, 0V and 0V, for example, are applied to the drain electrode 62, the gate electrode 63, the source electrode 64 and a substrate 65, respectively. As a result of applying such voltages, a reverse bias is applied between the drain and the substrate, so that a depletion layer is formed in the vicinity of the drain. Further, because the voltage of the drain electrode 62 is higher than a substrate voltage, a distance between a P-type valence band of the substrate 65 and an N-type conduction band of the drain electrode 62 becomes extremely small. This allows the P-type electrons in the substrate 65 to pass through the depletion layer surrounding the drain electrode 62 and move to the N-type conduction band of the drain electrode 62, so that current flows from the drain electrode 62 to the substrate 65. Furthermore, current increases rapidly as a voltage difference between the drain electrode 62 and the substrate 65 becomes larger. In addition, when the electrons which move from the P-type region of the substrate 65 to the drain electrode 62 pass through the depletion layer, they obtain a large energy due to a high electric field that is generated by a voltage between the drain electrode 62 and the substrate 65. Thus, secondary electrons and holes are generated due to the collision upon entry into the drain electrode 62. The generated holes are hot holes which have a large energy due to a high electric field in the depletion layer. The hot holes are injected into the gate electrode side by a gate voltage. As a result of the injection of the holes into the nitride film 61 in which the electrons are accumulated, the electrons and the holes are combined together. In this way, erasing ends.
However, the holes are also injected into the nitride film in the vicinity of the drain in the erasing of a related art. If the position of the trapped hot electron and the position of the injected hole do not correspond, the trapped hot electrons cannot be erased completely. Further, after a certain period of time is elapsed from erasing, the holes and the electrons move slowly to combine with each other (cf. FIG. 30). Thus, a threshold of the memory cell becomes higher after erasing (cf. FIG. 31). As the threshold of the memory cell becomes higher, current of a memory cell transistor decreases gradually. Thus, the reactivity of a read circuit becomes lower, which results in the reduction of a read speed. In this manner, the threshold of the memory cell (the current of the memory cell) changes after writing and erasing according to a related art. A measure to reduce the change in the threshold of the memory cell which occurs after writing and erasing is disclosed in Japanese Unexamined Patent Application Publication No. 2005-317191.
The technique which is disclosed in Japanese Unexamined Patent Application Publication No. 2005-317191 applies a very low voltage to an upper electrode (gate) existing above an insulating film, in which electrons are trapped, immediately after writing in order to ensure a uniform state of the electrons trapped in the insulating film. The insulating film is a nitride film or the like. The electrons which have been concentrated in the vicinity of the drain during writing are thereby distributed uniformly. This technique creates a balanced state in which electrons hardly move immediately after writing, thereby reducing the change in the threshold of the memory cell with time immediately after writing.
Further, the technique applies a very low voltage to the gate electrode above the insulating film after erasing. The electrons which are not erased during the erase operation or the trapped electrons are thereby immediately combined with the holes, so that the state where the electrons and the holes move slowly after a certain period of time from erasing and the electrons are erased due to the combination of the electrons with the holes is already completed immediately after erasing. It is thereby possible to minimize the change in the threshold of the memory cell after erasing of the memory cell.
The technique which is disclosed in Japanese Unexamined Patent Application Publication No. 2001-93995 describes that the threshold of the memory cell appears differently depending on the position of the electron to be trapped in the insulating film during writing of the memory cell. Using such appearance of the threshold, this technique detects the direction of current flowing to the memory cell and the threshold and reads multi-valued information stored in the memory cell based on the detected information.
However, because the technique of Japanese Unexamined Patent Application Publication No. 2005-317191 needs to apply a very low voltage to the gate of the memory cell immediately after writing or after erasing, it requires a longer operating time for writing and erasing. Further, because the technique also needs to prepare a circuit to generate a very low voltage to be applied to the gate of the memory cell immediately after writing and erasing, it requires a larger circuit size.